1. Field of the Invention
The present invention relates in general to a repairing method, more specifically, to a repairing scheme for the reduction of extra standby current induced by process defects.
2. Description of the Related Art
As the portable electronic products such as notebook computers, cellular phone, and personal digital agency (PDA) are widely used, the demands of static random access memory (SRAM) are also increasing. In order to prolong the life of the battery used by the portable electronic products, generally the integrated circuits (ICs) must meet the requirement for low power consumption. To achieve the object, the ICs are designed to have a small standby current, thereby reducing the unnecessary power consumption.
FIG. 1 illustrates the structure of a conventional SRAM. In FIG. 1, C1, C2.about.Cn represent the memory cells of SRAM; WL1, WL2.about.WLn represent the word lines; BL, BLB are bit lines (bit-line and bit-line bar); and Q1, Q2 are pull-up transistors which are always kept in an on state. The bit lines BL and BLB may be shorted to the ground (for example Vss) due to the process defects such as metal defects, etc. Although using redundancy can repair those defects, there are still some problems. Since the pull-up transistors in a cell are always on, therefore a leakage current (about 1.about.2 mA in general) may flow through bit lines to the ground, even if other defects are repaired. The leakage currents may not influence the logic function of SRAM, however, the SRAM will consume a great amount of power even in a standby state. So the SRAM will be picked out in a standby current test. A minority of the above current defects will induce a total standby current over the specification, and the whole chip will be discarded, even though the logic function of SRAM is correct. Consequently, the yield is reduced, and the cost is raised.